晶體(ti)元(yuan)件(jian)的(de)負載電(dian)(dian)(dian)容(rong)(rong)(rong)是指(zhi)在(zai)電(dian)(dian)(dian)路中跨(kua)接(jie)晶體(ti)兩端(duan)的(de)總的(de)外界有效電(dian)(dian)(dian)容(rong)(rong)(rong)。是指(zhi)晶振要(yao)正(zheng)常震蕩所需要(yao)的(de)電(dian)(dian)(dian)容(rong)(rong)(rong)。一(yi)般外接(jie)電(dian)(dian)(dian)容(rong)(rong)(rong),是為了使(shi)晶振兩端(duan)的(de)等(deng)(deng)效電(dian)(dian)(dian)容(rong)(rong)(rong)等(deng)(deng)于(yu)或接(jie)近負載電(dian)(dian)(dian)容(rong)(rong)(rong)。要(yao)求高(gao)的(de)場合(he)還要(yao)考(kao)慮ic輸入(ru)端(duan)的(de)對地電(dian)(dian)(dian)容(rong)(rong)(rong)。應(ying)用時一(yi)般在(zai)給出負載電(dian)(dian)(dian)容(rong)(rong)(rong)值(zhi)附(fu)近調(diao)整可(ke)以得到精(jing)確頻率(lv)。此電(dian)(dian)(dian)容(rong)(rong)(rong)的(de)大小(xiao)主要(yao)影響負載諧(xie)(xie)振頻率(lv)和等(deng)(deng)效負載諧(xie)(xie)振電(dian)(dian)(dian)阻(zu)。
晶振的(de)負載電(dian)(dian)容(rong)(rong)=[(Cd*Cg)/(Cd+Cg)]+Cic+△C式中Cd,Cg為分別接在晶振的(de)兩個(ge)腳上和(he)對地(di)的(de)電(dian)(dian)容(rong)(rong),Cic(集(ji)成電(dian)(dian)路內部電(dian)(dian)容(rong)(rong))+△C(PCB上電(dian)(dian)容(rong)(rong)).就是說負載電(dian)(dian)容(rong)(rong)15pf的(de)話,兩邊個(ge)接27pf的(de)差不多了,一般a為6.5~13.5pF
各種邏輯芯(xin)片(pian)的(de)(de)(de)(de)(de)(de)晶(jing)振(zhen)(zhen)引腳可(ke)(ke)以(yi)(yi)(yi)等(deng)效為(wei)電(dian)(dian)(dian)容(rong)三點(dian)(dian)(dian)式振(zhen)(zhen)蕩(dang)(dang)(dang)器(qi)(qi)。晶(jing)振(zhen)(zhen)引腳的(de)(de)(de)(de)(de)(de)內部(bu)通(tong)(tong)常是(shi)(shi)(shi)(shi)(shi)(shi)(shi)一(yi)個(ge)(ge)(ge)反(fan)(fan)相器(qi)(qi), 或者(zhe)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)奇(qi)數(shu)個(ge)(ge)(ge)反(fan)(fan)相器(qi)(qi)串聯。在(zai)晶(jing)振(zhen)(zhen)輸(shu)(shu)(shu)(shu)出(chu)引腳 XO 和(he)(he)晶(jing)振(zhen)(zhen)輸(shu)(shu)(shu)(shu)入引腳 XI 之(zhi)間用一(yi)個(ge)(ge)(ge)電(dian)(dian)(dian)阻連(lian)接(jie), 對于 CMOS 芯(xin)片(pian)通(tong)(tong)常是(shi)(shi)(shi)(shi)(shi)(shi)(shi)數(shu) M 到數(shu)十(shi) M 歐之(zhi)間。很(hen)多芯(xin)片(pian)的(de)(de)(de)(de)(de)(de)引腳內部(bu)已經(jing)包含了(le)這(zhe)個(ge)(ge)(ge)電(dian)(dian)(dian)阻, 引腳外部(bu)就(jiu)(jiu)不用接(jie)了(le)。這(zhe)個(ge)(ge)(ge)電(dian)(dian)(dian)阻是(shi)(shi)(shi)(shi)(shi)(shi)(shi)為(wei)了(le)使反(fan)(fan)相器(qi)(qi)在(zai)振(zhen)(zhen)蕩(dang)(dang)(dang)初始時(shi)處與線性(xing)狀(zhuang)態, 反(fan)(fan)相器(qi)(qi)就(jiu)(jiu)如同一(yi)個(ge)(ge)(ge)有(you)很(hen)大增益(yi)的(de)(de)(de)(de)(de)(de)放大器(qi)(qi), 以(yi)(yi)(yi)便于起振(zhen)(zhen)。石(shi)英(ying)晶(jing)體也連(lian)接(jie)在(zai)晶(jing)振(zhen)(zhen)引腳的(de)(de)(de)(de)(de)(de)輸(shu)(shu)(shu)(shu)入和(he)(he)輸(shu)(shu)(shu)(shu)出(chu)之(zhi)間, 等(deng)效為(wei)一(yi)個(ge)(ge)(ge)并聯諧(xie)(xie)振(zhen)(zhen)回路, 振(zhen)(zhen)蕩(dang)(dang)(dang)頻(pin)率(lv)應該是(shi)(shi)(shi)(shi)(shi)(shi)(shi)石(shi)英(ying)晶(jing)體的(de)(de)(de)(de)(de)(de)并聯諧(xie)(xie)振(zhen)(zhen)頻(pin)率(lv)。晶(jing)體旁(pang)邊的(de)(de)(de)(de)(de)(de)兩個(ge)(ge)(ge)電(dian)(dian)(dian)容(rong)接(jie)地, 實際(ji)上(shang)就(jiu)(jiu)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)電(dian)(dian)(dian)容(rong)三點(dian)(dian)(dian)式電(dian)(dian)(dian)路的(de)(de)(de)(de)(de)(de)分(fen)壓電(dian)(dian)(dian)容(rong), 接(jie)地點(dian)(dian)(dian)就(jiu)(jiu)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)分(fen)壓點(dian)(dian)(dian)。以(yi)(yi)(yi)接(jie)地點(dian)(dian)(dian)即分(fen)壓點(dian)(dian)(dian)為(wei)參考點(dian)(dian)(dian), 振(zhen)(zhen)蕩(dang)(dang)(dang)引腳的(de)(de)(de)(de)(de)(de)輸(shu)(shu)(shu)(shu)入和(he)(he)輸(shu)(shu)(shu)(shu)出(chu)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)反(fan)(fan)相的(de)(de)(de)(de)(de)(de), 但(dan)(dan)從并聯諧(xie)(xie)振(zhen)(zhen)回路即石(shi)英(ying)晶(jing)體兩端來看, 形成一(yi)個(ge)(ge)(ge)正反(fan)(fan)饋(kui)以(yi)(yi)(yi)保證電(dian)(dian)(dian)路持續振(zhen)(zhen)蕩(dang)(dang)(dang)。在(zai)芯(xin)片(pian)設計時(shi), 這(zhe)兩個(ge)(ge)(ge)電(dian)(dian)(dian)容(rong)就(jiu)(jiu)已經(jing)形成了(le), 一(yi)般是(shi)(shi)(shi)(shi)(shi)(shi)(shi)兩個(ge)(ge)(ge)的(de)(de)(de)(de)(de)(de)容(rong)量(liang)相等(deng), 容(rong)量(liang)大小依工藝和(he)(he)版(ban)圖而不同, 但(dan)(dan)終歸(gui)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)比(bi)較小, 不一(yi)定(ding)適合很(hen)寬的(de)(de)(de)(de)(de)(de)頻(pin)率(lv)范(fan)圍。外接(jie)時(shi)大約是(shi)(shi)(shi)(shi)(shi)(shi)(shi)數(shu) PF 到數(shu)十(shi) PF, 依頻(pin)率(lv)和(he)(he)石(shi)英(ying)晶(jing)體的(de)(de)(de)(de)(de)(de)特性(xing)而定(ding)。需要注意的(de)(de)(de)(de)(de)(de)是(shi)(shi)(shi)(shi)(shi)(shi)(shi):這(zhe)兩個(ge)(ge)(ge)電(dian)(dian)(dian)容(rong)串聯的(de)(de)(de)(de)(de)(de)值(zhi)是(shi)(shi)(shi)(shi)(shi)(shi)(shi)并聯在(zai)諧(xie)(xie)振(zhen)(zhen)回路上(shang)的(de)(de)(de)(de)(de)(de), 會影響振(zhen)(zhen)蕩(dang)(dang)(dang)頻(pin)率(lv)。當兩個(ge)(ge)(ge)電(dian)(dian)(dian)容(rong)量(liang)相等(deng)時(shi), 反(fan)(fan)饋(kui)系(xi)數(shu)是(shi)(shi)(shi)(shi)(shi)(shi)(shi) 0.5, 一(yi)般是(shi)(shi)(shi)(shi)(shi)(shi)(shi)可(ke)(ke)以(yi)(yi)(yi)滿足振(zhen)(zhen)蕩(dang)(dang)(dang)條件的(de)(de)(de)(de)(de)(de), 但(dan)(dan)如果不易(yi)起振(zhen)(zhen)或振(zhen)(zhen)蕩(dang)(dang)(dang)不穩定(ding)可(ke)(ke)以(yi)(yi)(yi)減小輸(shu)(shu)(shu)(shu)入端對地電(dian)(dian)(dian)容(rong)量(liang), 而增加輸(shu)(shu)(shu)(shu)出(chu)端的(de)(de)(de)(de)(de)(de)值(zhi)以(yi)(yi)(yi)提高反(fan)(fan)饋(kui)量(liang)。
設計考慮(lv)事項:
1、使晶(jing)振、外部(bu)電(dian)容(rong)器(如果有)與 IC之間的信號線盡(jin)可能保持短。當非常低(di)的電(dian)流通過IC晶(jing)振振蕩器時,如果線路(lu)太長,會使它對 EMC、ESD 與串擾(rao)產生非常敏感(gan)的影響。而且長線路(lu)還(huan)會給振蕩器增(zeng)加寄生電(dian)容(rong)。
2、盡可能(neng)將其它時鐘線路(lu)與頻繁(fan)切換的信號線路(lu)布置(zhi)在(zai)遠離晶振連接的位置(zhi)。
3、當(dang)心晶振(zhen)和地(di)的走線(xian)
4、將(jiang)晶振外(wai)殼接(jie)地
如果實際的(de)(de)(de)負載電容配(pei)置(zhi)不(bu)當(dang),第(di)一會引起線路參(can)考頻(pin)(pin)率的(de)(de)(de)誤差。另外如在發射接收(shou)電路上會使晶振的(de)(de)(de)振蕩幅度下降(jiang)(不(bu)在峰點),影(ying)響混頻(pin)(pin)信號的(de)(de)(de)信號強度與(yu)信噪。
當波形出(chu)現削峰,畸變時,可增加負載電(dian)阻調整(zheng)(幾十K到幾百(bai)K).要(yao)穩定(ding)波形是(shi)并(bing)聯一個1M左(zuo)右的反(fan)饋電(dian)阻。